Fabrication of multilayer conductor structures on a semiconductor substrate involves deposition of a planar conductor pattern and a covering dielectric film for each layer of the multilayer structure. In addition, the stacked layers are interconnected by vertical conductors between the layers. These require formation of vertical holes or vias through the overlying dielectric layer to expose a portion or face of the underlying conductor, followed by formation of a conductor in the via. Formation of the conductor in the via is difficult because the via is a small (65 nm or less) high aspect ratio opening (e.g., one in which the depth is twice the diameter). Moreover, a barrier layer, an adhesion layer and a seed layer must first be deposited on the via surfaces before the conductor is deposited to fill the via. If the conductor is copper, then a thin film barrier layer of tantalum nitride is deposited on the dielectric surfaces of the via or opening, (to block migration of copper atoms), a thin film tantalum adhesion layer is deposited over the barrier layer and a thin film copper seed layer is deposited over the adhesion layer. Thereafter, copper is deposited to fill the via to form the vertical interlayer conductor.
The via or vertical opening is formed by a dielectric etch step that exposes a portion of the planar conductor at the bottom of the via. This step leaves residue of the etched dielectric material on the surface of the planar conductor exposed at the bottom of the via. In order to obtain electrical contact between the vertical interlayer conductor and the planar conductor, formation of the vertical conductor must be preceded by a thorough removal of the dielectric residue from the exposed surface of the planar conductor at the bottom of the via. This removal step may be referred to as a “preclean” step and is typically carried out by sputter etching in an inert species plasma (e.g., an argon plasma). The removed or sputtered residue accumulates on the chamber interior surfaces and is therefore not redeposited on the wafer. This preclean step is preferably carried out with sufficient plasma ion density to achieve an etch (removal) rate of about 300 to 500 Å/min. This requires a high plasma ion density, which is readily achieved with an inductively coupled plasma. For this purpose, the preclean step is carried out in a reactor chamber depicted in FIG. 1 having an inductive coil 10 overlying a ceiling 12 and an RF source 14 (e.g., 2 MHz) coupled to the coil 10 through an impedance match 15. In order to guarantee plasma ions reach the bottom of each via to clean the exposed planar conductor surface, a high frequency bias voltage source 16 (e.g., 13.56 MHz) is coupled through an impedance match 17 to a wafer support pedestal 18 that faces the ceiling 12. The ceiling 12 must be formed of a non-conductor, such as quartz, to permit power to be inductively coupled through it from the coil 10 into the chamber interior. A process gas supply 19 furnishes an inert gas such as argon into the chamber interior.
FIG. 2 depicts a cross-sectional view of a portion of the wafer surface immediately prior to the preclean step. A planar copper conductor 20 lies in a trench formed in an underlying dielectric layer 22 and is covered by an overlying dielectric layer 24. A via 26 is formed by a dielectric etch step as a high aspect ratio opening. A small portion of the insulating material etched from the overlying dielectric layer 24 during the etch step contributes to a thin residue or film 28 covering the otherwise exposed top surface of the planar conductor 20. During the preclean step, a wafer 30 is placed on the pedestal 18 and argon gas (for example) is introduced into the reactor chamber of FIG. 1 from the process gas supply 19. RF plasma source power is applied by the RF generator 14 to the coil 10 to generate a high density plasma in the chamber and RF plasma bias power is applied by the RF source 16 to the wafer pedestal to create sufficient bias voltage on the wafer to realize an etch rate of 300 Å/min at the exposed surface of the planar conductor 20 at the bottom of the via 26 (FIG. 2). The residue that is sputtered during this step migrates upwardly through the via 26 and eventually is deposited or captured on chamber interior surfaces. The residue that is thus deposited on the interior surface of the ceiling 12 must adhere to the ceiling 12 until removal of the wafer 30 from the chamber upon completion of the preclean step. Otherwise, the reside may fall back onto the wafer and contaminate it. Conventionally, the dielectric layer 24 was silicon dioxide, producing a silicon dioxide residue that readily adheres to the interior surface of the quartz ceiling 12. The interior surface of the quartz ceiling 12 may be roughened by grit blasting (for example) to enhance the adhesion of the residue and avoid flaking of the residue from the ceiling otherwise caused by temperature variations of the ceiling during processing. The roughness of the quartz ceiling interior surface may be increased to an arithmetic mean surface roughness (RA) value of 150 without cracking the quartz. Higher RA values may crack the quartz, which would make the residue film deposited on the ceiling more vulnerable to flaking from temperature variations. The RA value may be measured with a conventional profilometer and corresponds to the arithmetic mean ratio between minimum and maximum peak heights on the surface. Such a reactor performs well with silicon dioxide residues, the quartz ceiling providing excellent adhesion of the silicon dioxide residue.
One disadvantage is that the interior surface of the quartz ceiling 12 becomes less rough during repetitive use and must be removed, cleaned and roughened again. Eventually the quartz ceiling or dome 12 must be replaced, incurring a significant cost.
The latest generation of integrated circuits employ high performance dielectric materials as the interlayer insulator layer 24 of FIG. 2. The residue 28 produced during the preclean sputter etching of such materials can contain SiON, SiOC:N, polymide or other compositions, all of which have very poor adhesion to the interior surface of the quartz ceiling 12 compared to silicon dioxide residues of the earlier conventional structures. As a result, the residue captured on the interior surface of the ceiling 12 during the preclean step tends to flake off the ceiling 12 and onto the wafer 30 during processing. This problem cannot be solved by increasing the roughness of the quartz ceiling interior surface beyond RA 150 or RA 200 because the quartz material would crack.